The present invention relates to counters and, more particularly, to a look ahead terminal counter circuitry for reducing propagation delays within the counter network and eliminating false output signals due to transient conditions within the counter network.
Generally, a counter is a device capable of changing from one to another distinguishable state. Counters are operative to change states, and thereby produce one or more output signals, upon receipt of some predetermined number of input pulses. A plurality of counter stages are frequently cascaded together to perform digital counting. A component such as a register is used to generate and store counter output signals representative of the number of input pulses, or the number of occurrences of a particular event of interest. Outputs from the registers can be connected to associated combinational logic that is constructed to generate a state decode output signal when the register outputs are at predetermined states, e.g., when all the register outputs are at a one state, commonly known as terminal count. It is to be understood, however, that different combinational logic can be used to generate a state decode output signal when the register outputs are at any predetermined state.
Thus, as used hereinafter, the signal terminal count (TC) shall be used generally to represent a state decode output signal generated in response to register outputs at any predetermined state.
Counters are frequently used in computer networks, in combination with a variety of different types of combinational logic to perform numerical functions that allow the computer to solve problems relating to combinations, permutations and/or selection of discrete data from a large pool of input data.
For example, various types of combinational logic may be interconnected with counter networks to analyze the various ways in which discrete objects may be combined and permuted. One might wish to select r objects from n distinct objects for repetitive selection of the same object. In less technical terms, the combinational logic and an associated counter network can operate to sort a large volume of input data into definable groups having some common characteristics. One such application would be to segregate components of radar return signals indicative of the presence of a moving target, or to segregate incident x-ray signals having signal components representative of the existence of cancerous growths in a patient. Such applications typically require a generation of complex signals representative of numerical functions, combination of input data with those functions and an analysis of the recurrence of predetermined signal patterns within the combination. Circuitry to perform those functions include complex combinational logic and an extended number of counters operatively associated with that combinational logic.
Frequently counter networks and combinational logic are not segregatable with respect to testing procedures such that it is impossible to differentiate between a failure in the combinational logic and a failure in the counter network. Moreover, a plurality of counter stages may be "buried" within a larger circuit such that it is almost impossible to identify where any failure may be located. Additionally, where the counter must be sequenced through its entire operational cycle to generate an output signal, the time necessary to perform such a test may be unacceptably long and the information obtained from the test procedure may be limited to simple determination of whether the overall network performs as desired, without any differentiation regarding the source of any failure. Furthermore, as explained below, such a test will not necessarily identify failures that may appear at states other than the final state of the counter network. Consequently, the information obtained from such contemporary testing procedures is too little, and the time necessary to obtain that information is too long.
In order to facilitate the testing of counters utilized in digital processing systems it is customarily necessary to apply a large number of clock pulses to the counter circuit and determine whether counter signals are being correctly generated in response to the appropriate number of clock pulses. In some cases it may be sufficient to confirm that the terminal count output of the counter network occurs after the correct number of clock pulses, i.e. that the counter network generates a terminal count output signal at the counter network cycle rate. However, as is well understood by those familiar with counter networks, a check of only the terminal count output signal does not insure that each individual counter register is operating correctly. This failure of individual counter register may result in the loss of information from combinational logic associated with an inoperative counter register, and the loss of intermediate output signals from the counter network. Such failures may, for example, occur where the output of one or more counter registers is stuck at a high level, and may not be detectable by a simple examination of the terminal count output of the counter network. Accordingly, it is frequently necessary to examine the output of each individual counter register after each clock pulse during one cycle. This procedure may be not only time consuming, but may also require an inordinate amount of dedicated storage and comparison circuitry. Where a plurality of counter stages are cascaded it is even more time consuming to compare the state of each counter register with the expected state after each clock pulse and counter enable pulses associated with a cycle of the counter, i.e. network cycle time.
Aside from failures associated with stuck counter registers, failures may result where the counter network, though operative to properly effect state changes in response to input signals, fails to enable generation of a terminal count signal soon enough after the appropriate clock pulse. Such failures are commonly referred to as race conditions. Other failures occur where, due to transient conditions within the counter network, a terminal count signal is generated at an inappropriate time. A brief explanation of how such false terminal count signals may be generated is believed to be useful for a more complete understanding of the present invention.
As previously indicated a counter network typically operates to generate a terminal count signal each time the counter network sequences through a predetermined number of clock pulses. After each counter register is sequenced to a desired output state, logic forming a portion of the counter network recognizes the existence of the desired state condition at each counter register and enables generation of a terminal count signal upon occurrence of the next clock pulse. Difficulties arise where, due to factors such as inherent propagation delays in the circuit components, the output state of the counter registers may briefly be in a state that enables the generation of a terminal count signal, though the counter has not yet received the desired number of input pulses. Consequently, if the next clock pulse occurs prior to the time the counter registers have completed transitioning to states corresponding to the current count, a false terminal count signal may be generated from the counter.
Thus, in addition to providing an improved technique for testing the operation of the counter and associated combinational logic the present invention is also directed to circuitry for reducing counter propagational delays and eliminating false output signals, associated with terminal count, as described more fully below.
Accordingly, the present invention is directed to a counter wherein each counter register may be separately tested without the need to sequence all counter registers and counter enable circuitry through the number of clock pulses corresponding to the network cycle time. The present invention further provides a counter network wherein an error may be resolved to a specific register or to combinational logic associated with a specific register. The present invention also provides a counter network wherein propagation delays and false output signals associated with terminal count can be reduced or eliminated. The counter network of the present invention is also intended to permit operation of the counter in a plurality of modes including a counting mode, a testing mode, a hold mode, a clear mode and a data loading mode, thereby rendering the counter network more versatile, more testable and more reliable.